1. Field of the Invention
The present invention relates to a method and apparatus for receiving serial data, and more particularly, to a method and apparatus for receiving serial digital data even when a sync signal or a block address of the data is lost.
2. Description of the Related Arts
When serial data is stored in a recording medium or transmitted in units of one block, a sync signal is inserted at the head of each block to divide the serial data into blocks. The sync signal is desired to have a pattern which is not found in the source data so that the sync signal is correctly detected in a reproducing or receiving part.
However, when both analog video signals and digital video signals are recorded on a recording medium at the same time, the probability increases that the code pattern of the data used as the sync signal is duplicated in the source data, in turn increasing the probability of error due to erroneous sync signal detection. Lengthening the sync signal data may decrease the probability of error, but it also decreases the recordable frequency band and data transmission speed.
FIG. 1A shows a typical format of one block of serially transmitted digital data. The depicted format includes a sync signal SYNC, an ID code ID, a block address code BA, an error correction code EDC, and serial digital data D0, . . . , Dn. ID code ID and block address code BA are included in addition to sync signal SYNC so that parity checking can be performed in order to decrease the probability of errors.
An apparatus for detecting a sync signal in data transmitted with such a format is disclosed in U.S. Pat. No. 5,228,041 issued Jul. 13, 1993 to Yoshino et al. and entitled "SYNC SIGNAL DETECTION SYSTEM IN A MEMORY SYSTEM FOR RECORDING AND REPRODUCING BLOCK UNIT DATA". In the apparatus of Yoshino et al., whenever a sync signal is detected, a block address is incremented or decremented. If the resultant value is identical to the transmitted block address, and if parity testing is performed using the ID code (ID) and the block address code (BA) indicates that the detected sync signal is correct, the value of the block address counter is output.
When the parity test for the ID code ID and the block address code BA is successful but the transmitted block address and the incremented block address are not identical (e.g. when one or more normal sync signals are not detected due to noise and the block address counter is not incremented), the transmitted block address is applied to the block address counting circuit and then output to adjust a memory address.
Generally, when serial data which is transmitted in block units with a sync signal, the following errors may take place. First, when the source data has a code pattern that is the same as that of the sync signal, a sync signal detection error may occur. Second, when the sync signal is lost or changed due to noise, the source data itself may be ignored.
While the first error can be cured by the apparatus of Yoshino et al., the second error can not. Specifically, the prior art has the problem of losing a transmitted data block when the associated sync signal can not be detected.
Meanwhile, even though the above-mentioned prior art makes it possible to decrease the probability of error in sync signal detection without increasing the length of the sync signal, the transmitted block data must always also include codes such as an identification code, a block address, and an error detecting code, so that parity can be checked. Thus, another problem with the prior art is that unused memory space may exist when a track jump occurs since the block address is used in detecting the sync signal.
The above-mentioned prior art has yet another problem in that a clock line for latching data is required in addition to a line for receiving the block data.